CAT24FC01_05 Datasheet, PDF (4/10 Pages) Catalyst Semiconductor – 1-kb I2C Serial EEPROM

CAT24FC01
FUNCTIONAL DESCRIPTION
SDA: Serial Data/Address
The CAT24FC01 supports the I²C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
The CAT24FC01 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
any device that sends data to the bus to be a transmitter _{other open drain or open collector outputs.}
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which ^{A0, A1, A2: Device Address Inputs}
generates the serial clock and all START and STOP ^{These inputs set device address when cascading multiple}
conditions for bus access. The CAT24FC01 operates as ^{devices. A maximum of eight devices can be cascaded}
a Slave device. Both the Master and Slave devices can ^{when using the device.}
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
rt _{PIN DESCRIPTIONS}
a SCL: Serial Clock
The CAT24FC01 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input pin.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC01 when this pin is tied
to V_CC, the entire array of memory is write protected.
When left floating, memory is unprotected.
P _{Figure 1. Bus Timing tF}
d _SCL
e _tSU:STA
u _{SDA IN}
tin ^{SDA OUT}
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
on SCL
Disc ^SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1073, Rev. G
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice