CAT24FC01_05 Datasheet, PDF (6/10 Pages) Catalyst Semiconductor – 1-kb I2C Serial EEPROM

CAT24FC01
WRITE OPERATIONS
Byte Write
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
In the Byte Write mode, the Master device sends the ^{the CAT24FC01 in a single write cycle.}
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
Acknowledge Polling
the Slave generates an acknowledge, the Master sends ^{The disabling of the inputs can be used to take advantage}
the byte address that is to be written into the address ^{of the typical write cycle time. Once the stop condition}
pointer of the CAT24FC01. After receiving another ^{is issued to indicate the end of the host’s write operation,}
acknowledge from the Slave, the Master device transmits ^{the CAT24FC01 initiates the internal write cycle. ACK}
the data byte to be written into the addressed memory
location. The CAT24FC01 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
t _{nonvolatile memory. While this internal cycle is in}
r _{progress, the device will not respond to any request from}
the Master device.
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC01 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC01 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
a _{Page Write}
The CAT24FC01 writes up to 16 bytes of data in a single
P _{write cycle, using the Page Write operation. The Page}
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
d after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
e ^{been transmitted the CAT24FC01 will respond with an}
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
u _unchanged.
tin ^{If the Master transmits more than 16 bytes prior to}
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
WRITE PROTECTION
The CAT24FC01 is designed with a hardware protect
pin that enables the user to protect the entire memory.
Thehardware protection feature of the CAT24FC01 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC01 allows the user to protect against inadvertent
programming of the memory array. If the WP pin is tied
to Vcc, the entire memory array is protected and becomes
read only. The entire memory becomes write protected
regardless of whether the write protect register has been
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
n Figure 6. Byte Write Timing
S
o^T
BUS ACTIVITY: ^A
MASTER ^R
T
c_{SDA LINE S}
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
P
is ^A
A
A
C
C
C
K
K
K
D ^{Figure 7. Page Write Timing}
S
T
BUS ACTIVITY: ^A
SLAVE
MASTER ^R ADDRESS
T
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
DATA n+7 ^O
P
SDA LINE S
P
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1073, Rev. G
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice