CAT93C46_07 Datasheet, PDF (6/15 Pages) Catalyst Semiconductor – 1-Kb Microwire Serial EEPROM

CAT93C46
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be deselected
for a minimum of t_CSMIN. The falling edge of CS will start
the self clocking for auto-clear and data store cycles on
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN (Figure 5). The falling edge of CS will start the
self clocking clear cycle of the selected memory location.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46 can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical “1” state.
Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
contents of all memory bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN (Figure 7). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Write Instruction Timing
SK
CS
AN AN-1
DI
101
A0 _DN
D0
tCSMIN
STATUS
VERIFY
STANDBY
tSV
BUSY
tHZ
HIGH-Z
DO
READY
HIGH-Z
tEW
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
Doc No. 1106, Rev. F