CAT93C46_07 Datasheet, PDF (4/15 Pages) Catalyst Semiconductor – 1-Kb Microwire Serial EEPROM

CAT93C46
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ 50ns
0.4V to 2.4V
4.5V ≤ V_CC ≤ 5.5V
0.8V, 2.0V
4.5V ≤ V_CC ≤ 5.5V
0.2V_CC to 0.7V_CC
1.8V ≤ V_CC ≤ 4.5V
0.5V_CC
1.8V ≤ V_CC ≤ 4.5V
Current Source I_OLmax/I_OHmax; C_L=100pF
DEVICE OPERATION
The CAT93C46 is a 1024-bit nonvolatile memory in-
tended for use with industry standard microprocessors.
The CAT93C46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase opera-
tions of the device. When organized as X8, seven 10-bit
instructions control the reading, writing and erase
operations of the device. The CAT93C46 operates on
a single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status during a write operation. The serial
communication protocol follows the timing shown in
Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in appli-
cations where the DI pin and the DO pin are to be tied
together to form a common DI/O pin. The Ready/Busy
flag can be disabled only in Ready state; no change is
allowed in Busy state.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organization).
Read
Upon receiving a READ command (Figure 2) and an
address (clocked into the DI pin), the DO pin of the
CAT93C46 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t_PD0 or t_PD1).
Erase/Write Enable and Disable
The CAT93C46 powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled,
it will remain enabled until power to the device is removed,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C46 write and erase
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 3.
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
Address
x8
x16
A6-A0 A5-A0
A6-A0 A5-A0
A6-A0 A5-A0
11XXXXX 11XXXX
00XXXXX 00XXXX
10XXXXX 10XXXX
01XXXXX 01XXXX
Data
x8
x16
Comments
Read Address AN– A0
Clear Address AN– A0
D7-D0 D15-D0 Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc No. 1106, Rev. F