CAT5409 Datasheet, PDF (5/17 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometers (DPPTM) with 64 Taps and 2-wire Interface

CAT5409
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
tWR
Write Cycle Time
Min
Typ Max Units
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
N_END(1) Endurance
MIL-STD-883, Test Method 1033
T_DR(1)
Data Retention
MIL-STD-883, Test Method 1008
V_ZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015
I_LTH(1)(2) Latch-Up
JEDEC Standard 17
Min
Typ
1,000,000
100
2000
100
Max Units
Cycles/Byte
Years
Volts
mA
Figure 1. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
SCL
Note:
START BIT
STOP BIT
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
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Document No. 2010, Rev. I