CAT5409 Datasheet, PDF (1/17 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometers (DPPTM) with 64 Taps and 2-wire Interface

CAT5409
ALOGEN ^FR
Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and
2-wire Interface
FEATURES
LEAD
F
R
E
E
TM
s Four linear-taper digital potentiometers
s 64 resistor taps per potentiometer
s End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
s 2-wire interface (I²C like)
s Low wiper resistance, typically 80Ω
s Four non-volatile wiper settings for each
potentiometer
s Recall of saved wiper settings at power-up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC, 24-lead TSSOP and BGA
s Write protection for data register
DESCRIPTION
The CAT5409 is four Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP.
Associated with each wiper control register are four 6-
bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data registers
is via a 2-wire serial bus (I²C-like). On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The Write Protection (WP) pin protects against
inadvertent programming of the data register.
The CAT5409 can be used as a potentiometer or as
a two terminal, variable resistor. It is intended for
circuit level or system level adjustments in a wide
variety of applications.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC Package (J, W)
TSSOP Package (U, Y)
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴⁰⁹ 18
8
17
9
16
10
15
11
14
12
13
NC
RL3
RH3
RW3
A0
NC
A3
SCL
RL2
RH2
RW2
NC
SDA
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCL
A3
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴⁰⁹ 18
8
17
9
16
10
15
11
14
12
13
WP
A2
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
NC
RH0 RH1 RH2 RH3
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP
A0
A1
CONTROL
A2
LOGIC
A3
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
R _W0
R _W1
R _W2
R _W3
A
B
BGA C
D
E
F
1
RW0
RL0
VCC
NC
RL3
RW3
2
A2
WP
RH0
RH3
NC
A0
3
4
A1
RL1
SDA
RH1
RW1
VSS
RH2
A3
SCL
NC
RW2
RL2
Top View - Bump Side Down
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2010, Rev. I