CAT5269_07 Datasheet, PDF (5/16 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and 2-wire Interface

CAT5269
POWER UP TIMING ⁽¹⁾⁽²⁾
Symbol Parameter
t_PUR Power-up to Read Operation
t_PUW Power-up to Write Operation
Max Units
1
ms
1
ms
XDCP TIMING
Symbol
t_WRPO
t_WRL
Parameter
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
WRITE CYCLE LIMITS ⁽³⁾
Symbol Parameter
t_WR
Write Cycle Time
Min
Max Units
5
10
µs
5
10
µs
Max Units
5
ms
RELIABILITY CHARACTERISTICS
Symbol
N_END(1)
T_DR(1)
V_ZAP(1)
I_LTH(1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min Max
1,000,000
100
2000
100
Units
Cycles/Byte
Years
V
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are delays required from the time V_CC is stable until the specified operation can be initiated.
(3) The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Figure 1. Bus Timing
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA
tDH
tSU:STO
tBUF
© Catalyst Semiconductor, Inc.
5
Characteristics subject to change without notice
Doc. No. MD-2123 Rev. C