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CAT5269_07 Datasheet, PDF (4/16 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and 2-wire Interface
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CAT5269
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
ICC1
Power Supply Current
ICC2
Power Supply Current
Non-volatile WRITE
ISB
Standby Current (VCC = 5.0V)
fSCL = 400kHz, SDA = Open
VCC = 6V, Inputs = GND
fSCK = 400kHz, SDA Open
VCC = 6V, Input = GND
VIN = GND or VCC, SDA = Open
ILI
Input Leakage Current
VIN = GND to VCC
ILO
Output Leakage Current
VOUT = GND to VCC
VIL
Input Low Voltage
VIH
Input High Voltage
VOL1
VOL2
Output Low Voltage (VCC = 3.0V) IOL = 3mA
Output Low Voltage (VCC = 1.8V) IOL = 1.5mA
Min
-1
VCC x 0.7
Max
1
5
5
10
10
VCC x 0.3
VCC + 1.0
0.4
0.5
Units
mA
mA
µA
µA
µA
V
V
V
V
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
CI/O(1)
CIN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ¯W¯P¯)
Conditions
VI/O = 0V
VIN = 0V
Max Units
8
pF
6
pF
A.C. CHARACTERISTICS
Symbol Parameter
fSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Note:
This parameter is tested initially and after a design or process change that affects the parameter.
2.5V - 6.0V
Min
Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Doc. No. MD-2123 Rev. C
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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