CAT25C65 Datasheet, PDF (5/11 Pages) Catalyst Semiconductor – 32K/64K-Bit SPI Serial CMOS EEPROM

CAT25C33/65
SCK: Serial Clock
WP: Write Protect
SCK is the serial clock pin. This pin is used to synchro- WP is the Write Protect pin. The Write Protect pin will allow
nize the communication between the microcontroller normal read/write operations when held high. When WP is
and the 25C33/65. Opcodes, byte addresses, or data tied low and the WPEN bit in the status register is set to “1”,
present on the SI pin are latched on the rising edge of the all write operations to the status register are inhibited. WP
SCK. Data on the SO pin is updated on the falling edge going low while CS is still low will interrupt a write to the status
of the SCK.
register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the
status register. The WP pin function is blocked when the
CS: Chip Select
WPEN bit is set to 0.
CS is the Chip select pin. CS low enables the CAT25C33/ ^{HOLD: Hold}
65 and CS high disables the CAT25C33/65. CS high ^{The HOLD pin is used to pause transmission to the}
takes the SO output pin to high impedance and forces ^{CAT25C33/65 while in the middle of a serial sequence}
the devices into a Standby Mode (unless an internal ^{without having to re-transmit entire sequence at a later time.}
write operation is underway). The CAT25C33/65 draws ^{To pause, HOLD must be brought low while SCK is low. The}
ZERO current in the Standby mode. A high to low ^{SO pin is in a high impedance state during}
transition on CS is required prior to any sequence being ^{the time the part is paused, and transitions on the SI pins}
initiated. A low to high transition on CS after a valid write ^{will be ignored. To resume communication, HOLD is brought}
sequence is what initiates an internal write cycle.
high, while SCK is low. (HOLD should be held high any time
this function is not being used.) HOLD may be tied high
STATUS REGISTER
7
6
WPEN
X
5
4
3
2
1
0
X
BP2
BP1
BP0
WEL
RDY
MEMORY PROTECTION
BP2 BP1 BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
MEMORY PROTECTION
CAT25C33
Q1 0000-03FF
Q2 0400-07FF
Q3 0800-0BFF
Q4 0C00-0FFF
H1
0000-07FF
P0
0000-003F
Pn
0FC0-0FFF
CAT25C65
0000-07FF
0800-0FFF
1000-17FF
1800-1FFF
0000-0FFF
0000-003F
0FC0-1FFF
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
5
Doc No. 1000, Rev. F