CAT24WC164_1 Datasheet, PDF (4/13 Pages) Catalyst Semiconductor – 16K-Bit Serial EEPROM, Cascadable

CAT24WC164
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC164 supports the I²C Bus data SCL: Serial Clock
transmission protocol. This Inter-Integrated Circuit Bus The CAT24WC164 serial clock input pin is used to clock
protocol defines any device that sends data to the bus to all data transfers into or out of the device. This is an input
be a transmitter and any device receiving data to be a pin.
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
SDA: Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
operates as a Slave device. Both the Master and Slave
is used to transfer data into and out of the device. The
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
art ^{determined by the device address inputs A0, A1, and A2.}
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
P Figure 1. Bus Timing
tF
d _SCL
e tSU:STA
u _{SDA IN}
tin ^{SDA OUT}
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
n _SCL
Disco ^SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1026, Rev. J
4
STOP BIT