CAT5261_08 Datasheet, PDF (3/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and SPI Interface

CAT5261
SERIAL BUS PROTOCOL
The CAT5261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5261 to interface directly with
many of today's popular microcontrollers. The
DEVICE OPERATION
The CAT5261 is two resistor arrays integrated with an
SPI serial interface logic, two 8-bit wiper control
registers and eight 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R_H and R_L).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (R_W) by a After the device is selected with
¯C¯S¯ _{going low the first byte will be received. The part}
is accessed via the SI pin, with data being clocked in
on the rising edge of SCK. The first byte contains one
CAT5261 contains an 8-bit instruction register .The
instruction set and the operation codes are detailed in
the instruction set table 3 on page 9.
of the six op-codes that define the operation to be
performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper
control register. Data can be read or written to the
wiper control registers or the non-volatile memory
data registers via the SPI bus. Additional instructions
allows data to be transferred between the wiper
control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
© Catalyst Semiconductor, Inc.
3
Characteristics subject to change without notice
Doc. No. MD-2122 Rev. E