CAT5261_08 Datasheet, PDF (2/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and SPI Interface

CAT5261
PIN DESCRIPTIONS
SI: Serial Input
SI is the serial data input pin. This pin is used
to input all opcodes, byte addresses and data
to be written to the CAT5261. Input data is
latched on the rising edge of the serial clock.
Pin #
1
2
3
Name
SO
A0
NC
Function
Serial Data Output
Device Address, LSB
No Connect
SO: Serial Output
4
SO is the serial data output pin. This pin is
used to transfer data out of the CAT5261.
5
During a read cycle, data is shifted out on the
6
falling edge of the serial clock.
7
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
8
synchronize the communication between the
9
microcontroller and the CAT5261. Opcodes,
byte addresses or data present on the SI pin
10
are latched on the rising edge of the SCK. ₁₁
Data on the SO pin is updated on the falling
edge of the SCK.
12
NC No Connect
NC No Connect
NC No Connect
V_CC Supply Voltage
R_L0 Low Reference Terminal for Potentiometer 0
R_H0 High Reference Terminal for Potentiometer 0
R_W0 Wiper Terminal for Potentiometer 0
¯C¯S¯ Chip Select
¯W¯P¯ Write Protection
A0, A1: Device Address Inputs
13
These inputs set the device address when 14
addressing multiple devices. A total of four
devices can be addressed on a single bus. A
15
match in the slave address must be made ₁₆
with the address input in order to initiate
communication with the CAT5261.
17
SI Serial Input
A1 Device Address
R_L1 Low Reference Terminal for Potentiometer 1
R_H1 High Reference Terminal for Potentiometer 1
R_W1 Wiper Terminal for Potentiometer 1
R_H, R_L: Resistor End Points
18 GND Ground
The R_H and R_L pins are equivalent to the ₁₉
NC No Connect
terminal connections on a mechanical
potentiometer.
20
NC No Connect
R_W: Wiper
21
NC No Connect
The RW pins are equivalent to the wiper 22
NC No Connect
terminal of a mechanical potentiometer.
23 SCK Bus Serial Clock
¯C¯S¯: _{Chip Select}
¯C¯S¯ _{is the Chip select pin.} ¯C¯S¯ _{low enables}
24 H¯¯O¯L¯D¯ Hold
the CAT5261 and ^{¯C¯S¯} high disables the
CAT5261. ^{¯C¯S¯} high takes the SO output pin to high impedance and forces the devices into a Standby mode
(unless an internal write operation is underway). The CAT5261 draws ZERO current in the Standby mode. A high
to low transition on ^{¯C¯S¯} is required prior to any sequence being initiated. A low to high transition on ^{¯C¯S¯} after a
valid write sequence is what initiates an internal write cycle.
¯W¯P¯: _{Write Protect}
¯W¯P¯ _{is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When}
¯W¯P¯ _{is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register}
is allowed). ^{¯W¯P¯} going low while ^{¯C¯S¯} is still low will interrupt a write to the registers. If the internal write cycle has
already been initiated, ^{¯W¯P¯} going low will have no effect on any write operation.
H¯¯O¯L¯D¯: Hold
The H¯¯O¯L¯D¯ pin is used to pause transmission to the CAT5261 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause, H¯¯O¯L¯D¯ must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
ignored. To resume communication, H¯¯O¯L¯D¯ is brought high, while SCK is low. (H¯¯O¯L¯D¯ should be held high any
time this function is not being used.) H¯¯O¯L¯D¯ may be tied high directly to V_CC or tied to V_CC through a resistor.
¯W¯P¯: _{Write Protect Input}
The ^{¯W¯P¯} pin when tied low prevents non-volatile writes to the device (change of wiper control register is allowed)
and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 6 for
more details.
Doc. No. MD-2122 Rev. E
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice