CAT24FC64_05 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM

CAT24FC64
A.C. CHARACTERISTICS
V_CC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
VCC=2.5V - 5.5V
Min
Max
Units
F_SCL
t_AA
t ⁽²⁾
BUF
Clock Frequency
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can
Start
50
1300
t_HD:STA Start Condition Hold Time
600
t_LOW
Clock Low Period
1300
t_HIGH
Clock High Period
600
t_SU:STA
t
HD:DAT
d _tSU:DAT
e ^{t (2)}
R
t ⁽²⁾
F
u _tSU:STO
tin ^tDH
t_WR
t_SP
n _tSU;WP
o _tHD;WP
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppresssion (SDA, SCL)
WP Setup Time
WP Hold Time
600
0
100
600
50
600
1300
c _{Power-Up Timing (2)(3)}
is ^{Symbol Parameter}
Min
t_PUR Power-Up to Read Operation
D^{tPUW Power-Up to Write Operation}
400
kHz
900
ns
ns
t_ns
r_ns
Pa ^ns
ns
ns
ns
300
ns
300
ns
ns
ns
5
ms
50
ns
ns
ns
Typ Max
100
100
Units
µs
µs
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1046, Rev. K