CAT25C03_05 Datasheet, PDF (1/12 Pages) Catalyst Semiconductor – 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM

CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
s 10 MHz SPI compatible
s 1,000,000 program/erase cycles
s 1.8 to 6.0 volt operation
s 100 year data retention
s Hardware and software protection
s Low power CMOS technology
s SPI modes (0,0 & 1,1)*
ts s Commercial, industrial, automotive and extended
temperature ranges
r _DESCRIPTION
a _{The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit}
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
P _{advanced CMOS Technology substantially reduces}
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
d _{features a 32-byte page write buffer.The device operates}
via the SPI bus serial interface and is enabled though a
e Chip Select (CS). In addition to the Chip Select, the clock
s Self-timed write cycle
s 8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP
s 16/32-byte page write buffer
s Write protection
– Protect first page, last page, any 1/4 array or
lower 1/2 array
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C11/03/05/09/17 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
PIN CONFIGURATION
u _{MSOP Package (R, Z, GZ)* SOIC Package (S, V, GV)}
CS 1
tin ^{SO 2}
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 _SI
*CAT25C11/03 only
CS ¹
SO ²
WP ³
VSS 4
8 VCC
7 _HOLD
6 SCK
5 SI
DIP Package (P, L, GL)
CS ¹
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
TSSOP Package (U, Y, GY)
CS
1
SO 2
WP ³
VSS
4
8
VCC
7
HOLD
6
SCK
5 _SI
on ^{PIN FUNCTIONS}
Pin Name
Function
c _SO
SCK
Serial Data Output
Serial Clock
is WP
Write Protect
D^VCC
+1.8V to +6.0V Power Supply
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SO
I/O
SI
CONTROL
CS
EEPROM
WP
SPI
CONTROL
XDEC
ARRAY
VSS
Ground
HOLD
LOGIC
SCK
CS
Chip Select
BLOCK
SI
Serial Data Input
PROTECT
LOGIC
HOLD
NC
Suspends Serial Input
No Connect
DATA IN
STORAGE
* Other SPI modes available on request.
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1017, Rev. L