CAT24FC32A Datasheet, PDF (9/12 Pages) Catalyst Semiconductor – 32K-Bit Fast Mode I2C Serial CMOS EEPROM

CAT24FC32A
been transmitted, CAT24FC32A will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 32 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC32A in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24FC32A initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24FC32A is still busy with the
write operation, no ACK will be returned. If CAT24FC32A
has completed the write operation, an ACK will be
returned and the host can then proceed with the next
read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is connected to VCC, the entire memory
array is protected and becomes read only. The
CAT24FC32A will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received. The
WP input is sampled in the end of acknowledge pulse
after second address byte, accordingly with setup and
hold times relative to negative clock edge (Figure 2).
READ OPERATIONS
The READ operation for the CAT24FC32A is initiated in
the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Immediate/Current Address Read
The CAT24FC32A’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
Figure 10. Page Write Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15—A ₈
A7—A ₀
SDA LINE S
X XX X
A
A
A
C
C
C
K
K
K
X=Don't care bit
DATA
DATA n
S
T
DATA n+31
O
P
P
A
AA
A
C
CC
C
K
KK
K
Figure 11. Immediate Address Read Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
S
T
DATA
O
P
SDA LINE S
P
A
N
C
O
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
9
STOP
Doc. No. 1048, Rev. F