CAT24FC65 Datasheet, PDF (4/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection

CAT24FC65/66
FUNCTIONAL DESCRIPTION
The CAT24FC65/66 supports the I²C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24FC65/66
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
bottom/top (CAT24FC65/CAT24FC66)1/4 of memory
is write protected. When left floating, memory is
unprotected.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC65/66's may be
addressed on a single bus system. When the pins are
left unconnected, the default values are zero.
Figure 1. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 1047, Rev. H
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice