CAT24FC65 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection

CAT24FC65/66
A.C. CHARACTERISTICS
V_CC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
F_SCL
t_AA
t ⁽²⁾
BUF
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t
SU:DAT
t ⁽²⁾
R
t ⁽²⁾
F
t_SU:STO
t_DH
t_WR
t_SP
t_SU;WP
t_HD;WP
Clock Frequency
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppresssion (SDA, SCL)
WP Setup Time
WP Hold Time
VCC=2.5V - 5.5V
Min
Max
400
50
900
1300
600
1300
600
600
0
100
300
300
600
50
5
50
600
1300
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
Power-Up Timing ⁽²⁾⁽³⁾
Symbol Parameter
Min Typ Max Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
ms
1
ms
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1047, Rev. H