CM1223 Datasheet, PDF (9/13 Pages) California Micro Devices Corp – Industry First Low Capacitance ESD Protection Arrays w/Backdrive Protection

CM1223
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 6, which illus-
trates an example of a positive 8kV ESD pulse striking
an input channel. The 8kV ESD current pulse will divert
along the path as indicated in Figure 4, through the D1
diode and the Zener diode back to the ground rail.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. The CM1223 has a fast response time of
less than 1ns and low clamp voltage to handle this
pulse.
Similarly for negative ESD pulses, parasitic series
inductance from the V_N pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
The CM1223 has an integrated backdrive diode
between V_P and V_N to prevent backdrive current flow
from the powered sources.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges.
Additional Information
See also California Micro Devices Application Note
AP209, “Design Considerations for ESD Protection”, in
the Applications section at www.cmd.com.
V_P
POSITIVE SUPPLY
V_CC
One Channel of
CM1223
30A
0A
8kV ESD Pulse
PATH OF POSI-
TIVE ESD CUR-
RENT PULSE I_ESDD1
I/O pin
D₂
PATH OF NEGATIVE
ESD
LINE BEING PROTECTED
SYSTEM OR
CIRCUITRY
BEING
V_N
GROUND RAIL
CHASSIS GROUND
Figure 6. Application of Positive ESD Pulse between Input Channel and Ground
© 2006 California Micro Devices Corp. All rights reserved.
08/02/06
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