CM9107 Datasheet, PDF (8/10 Pages) California Micro Devices Corp – Triple-Output LDO for WLAN

PRELIMINARY
CM9107
Application Information (cont’d)
independent of the three LDOs and their control cir­
cuits, functioning as a supervisory circuit for the MAC/
Baseband microprocessor. The RESET circuit has
complimentary RST and RST push-pull outputs.
When the system is powered-up and V_IN reaches a
pre-set threshold, RESET waits for the programmed
time-period and then signals the microprocessor that
V_IN is stable. During system operation, V_IN is continu­
ously monitored, and if it drops below the preset
threshold, it tells the microprocessor to reset, thus pre­
venting loss of data.
The RESET signals are asserted when the V_IN supply
voltage drops below 2.63V and will remain asserted for
the adjustable RESET delay period, controlled by con­
necting an external capacitor on the CT pin. The
RESET delay period is 2.5ms/nF of CT pin capaci­
tance. At the end of the delay period, the RESET sig­
nals are released; RST goes low and RST goes high.
Refer to Figure 2. If V_IN drops below the RESET
threshold again, the RESET signal is re-asserted. The
reset delay and threshold hysteresis help assure valid
RESET signals in the presence of erratic V_IN behavior.
The maximum low output voltage is 0.3V at 1.6mA sink
current. Minimum high output voltage is 80% of V_IN.
The RESET circuit consumes less than 5µA quiescent
current.
20 μs delay
VIN
2.63V
Capacitor Selection
The CM9107’s LDOs have a wide stability region for a
range of output capacitance and ESR values. While
2.2µF will be sufficient for each LDO output, higher out­
put capacitance, such as 3.3µF, 4.7µF or 10µF, will
reduce output noise and over-shoot during load tran­
sients. Low ESR ceramic capacitors are ideally suited
for the outputs of the CM9107, with X5R and X7R
dielectrics being the most stable over voltage and tem­
perature, providing the best performance.
To reduce the noise generated by the bandgap circuit,
a 33nF, low ESR ceramic capacitor is recommended
from the CB1 pin to ground.
Load Transient
The input and output capacitors will effect the transient
load response. The input capacitor will reduce input
drop during load transients, improving response on all
outputs, while increased output capacitance improves
the individual LDO output’s load transient response.
Layout Issues
Input and output capacitors should be located close to
the device. For good thermal conduction, connections
to large areas of C_U should be provided on the PCB.
RST
RST
25 ms delay
(CT = 0.01 μF)
Figure 2. Reset Delay
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07/11/06