CM9107 Datasheet, PDF (7/10 Pages) California Micro Devices Corp – Triple-Output LDO for WLAN

PRELIMINARY
CM9107
Application Information
The CM9107 is a triple-output, low noise, low dropout
(LDO) linear voltage regulator with an integrated micro­
processor reset circuit. It provides a single-chip power
management solution for WLAN systems, providing the
fixed output voltages needed for popular wireless
chipsets. It has an input voltage range of 3.0V to 3.6V.
The device can supply 500mA output from LDO1
(1.8V), 300mA from LDO2 (2.84V) and 200mA from
the low-noise LDO3 (2.84V).
The CM9107 achieves its low dropout voltage by using
efficient, internal P-channel MOSFETs for each output.
The dropout voltage for LDO2 is less than 220mV at
300mA load. The dropout voltage for LDO3 is less than
200mV at 200mA load. The lower voltage output from
LDO1 assures sufficient headroom to deliver 500mA
once V_IN is above the undervoltage lockout point, typi­
cally 2.45V. The CM9107 has excellent line and load
regulation over the operating temperature range. The
LDO outputs allow the use of low cost, space-efficient
ceramic capacitors.
The LDO3 has exceptionally low output noise, and is
ideal for VCO power supplies. The WLAN’s VCO circuit
is very phase noise sensitive, and needs clean power
for reliable operation. At 10mA output, the noise den­
sity from 10Hz to 100kHz is typically less than
30µV_RMS when using a 2.2µF output capacitor. With a
10µF output capacitor, the noise density is typically
20µV_RMS.
+/-5% of their nominal regulation value. The PGOOD
pin will go low when any output is out of regulation due
to over-current dropout, or when thermal shutdown is
triggered.
The PGOOD pin has an internal pull-up resistor. In the
shutdown mode (SHDN and SHDN3 both low),
PGOOD goes high.
Shutdown Control and Power Up/Down
Sequence
The CM9107 provides two active low, shutdown control
pins, SHDN and SHDN3. SHDN controls both LDO1
and LDO2. LDO3 is independently controlled with
SHDN3. Each shutdown pin has internal pull-up resis­
tor to V_IN. Pulling the pins low shuts-down the appropri­
ate output.
When SHDN goes high, LDO1’s output will rise first.
Once LDO1’s output is above about 1.7V, LDO2’s out­
put will start to rise. When SHDN goes low, LDO2’s
output will drop first. When LDO2’s output drops below
about 2.7V, LDO1’s output will start to drop. Refer to
Figure 1.
SHDN
Protection
The CM9107 has independent over-current protection
for each LDO output, with current foldback. The mini­
mum over-current limit is 550mA for LDO1, 330mA for
LDO2, and 250mA for LDO3.
The CM9107 includes a thermal shutdown. If there is
excessive internal power dissipation due to an over
current condition, or a high V_IN-V_OUT differential, and
device’s junction temperature exceeds 150°C (typical),
the outputs are turned off. The LDOs are turned on
again after the junction temperature drops below
130°C.
VO1 _1.71V
1.80V
Power down
sequence
Power up
sequence
VO2
2.84V
2.70V
Figure 1. Power Sequencing
Power Good
The CM9107 provides a high power good signal
(PGOOD) if all three LDOs output voltages are within
Reset
The CM9107’s RESET circuit monitors the V_IN voltage
only, upstream of the LDOs. This circuit is completely
© 2006 California Micro Devices Corp. All rights reserved.
07/11/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: [phone] lFax: [phone] lwww.cmd.com
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