CM9107 Datasheet, PDF (2/10 Pages) California Micro Devices Corp – Triple-Output LDO for WLAN

PRELIMINARY
CM9107
Package Pinout
Pin 1
Marking
PACKAGE / PINOUT DIAGRAM
TOP VIEW
(Pins Down View)
BOTTOM VIEW
(Pins Up View)
RST 1
CT 2
SHDN 3
SHDN3 4
12 VO1
11 CB1
10 VO2
9 CC2
12
1
11
GND
2
PAD
10
3
9
4
Note: This drawing is not to scale.
CM9107-00QE
16-Lead TQFN Package (4mmx4mm)
LEAD(s)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
RST
CT
SHDN
SHDN3
VO3
CC3
GND3
GND
CC2
VO2
CB1
VO1
VIN
VIN3
PGOOD
PIN DESCRIPTIONS
DESCRIPTION
Reset bar pin. This is the inverse output of the RST signal pin (pin 16).
CT pin for setting the delay time for RST assert (2.5ms per nF).
Shutdown control input pin for LDO1 and LDO2. Active low, LDO1 and LDO2 will be off when
the pin is pulled low. Connect to V_IN when unused.
Shutdown control input pin for LDO3. Active low. Connect to V_IN when unused.
LDO3 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
This pin is used for testing. In the application it could be either floating or tied to ground
Ground pin for LDO3
Ground pin for LDO1, LDO2 and control circuit
This pin is used for testing. In the application it could be either floating or tied to ground
LDO2 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
Bypass capacitor pin for internal bandgap reference (typically 0.033µF low-ESR type).
LDO1 output pin (1.80V). Connect a low-ESR bypass capacitor of 2.2µF, minimum.
Power input pin for LDO2 and LDO3. Connect to a low-ESR bypass capacitor of 2.2µF,
minimum.
Power input pin for LDO3. Connect to Pin 13, on the PC board, very near the device.
Power good output pin with internal pull-up resistor to VIN, goes high when all 3 LDOs are in
regulation.
© 2006 California Micro Devices Corp. All rights reserved.
2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: [phone] lFax: [phone] lwww.cmd.com
07/11/06