CM8888 Datasheet, PDF (7/13 Pages) California Micro Devices Corp – CMOS INTEGRATED DTMF TRANCEIVER

CALIFORNIA MICRO DEVICES
CM8888/8888-2
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs to
two sixth order switched capacitor bandpass filters, the
bandwidths of which correspond to the low and high-
group frequencies as shown in Figure 5. The low-
group filter incorporates notches at 350 Hz and 440
Hz for excellent dial-tone rejection. Each filter output
is followed by a single-order switched capacitor filter
section which smoothes the signals prior to limiting.
Limiting is performed by high-gain comparators with
hysteresis to prevent detection of unwanted low-level
signals. The outputs of the comparators provide full-
rail logic swings at the incoming DTMF signals
frequencies.
Following the filter section is a decoder which employs
digital counting techniques to determine the
frequencies of the incoming tones, and to verify that
the incoming tones correspond to standard DTMF
frequencies. A complex averaging algorithm protects
against tone simulation by extraneous signals (e.g.
voice), while still providing tolerance to small
deviations in frequency. The averaging algorithm was
developed to ensure and optimum combination of
immunity to talk-off , as well as a tolerance to the
presence of two valid tones (sometimes referred to as
“signal condition” in industry publications), the “Early
Steering” (EST) output will go to and active state. Any
subsequent loss of signal condition will cause ESt to
assume and inactive state.
SteeringCircuit
Before registration of a decoded tone pair, the receiver
checks for a valid signal duration (referred to as
Character Recognition Condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes VC (See Figure 3) to
rise as the capacitor discharge. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (tGTP), VC reaches the threshold
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (See Figure 5)
into the Receive Data Register. At this point the GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the Delayed Steering output flag goes high,
signalling that a received tone pair has been registered.
It is possible to monitor the status of the Delayed
Steering flag by checking the appropriate bit in the
Status Register. If Interrupt Mode has been selected,
the IRQ/CP pin will pull low when the Delayed Steering
flag is active.
The contents of the output latch are updated on an active
Delayed Steering transition. This data is presented to the
4-bit bi directional data bus when the Receive Data
Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as
well as rejecting signals too short to be considered valid,
the receiver will tolerate signal interruptions (drop out)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
VOLTAGE GAIN
Figure 1. Single Ended Input _{Configuration}
Figure 2. Differential Input _{Configuration}
© 2000 California Micro Devices Corp. All rights reserved.
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215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com
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