CM8888 Datasheet, PDF (11/13 Pages) California Micro Devices Corp – CMOS INTEGRATED DTMF TRANCEIVER

CALIFORNIA MICRO DEVICES
CM8888/8888-2
data transfer operations. The Receive Data Register contains
the output code of the last valid DTMF tone pair to be
decoded and is a read-only register. The data entered in
the Transmit Data Register will determine which tone
pair is to be generated (See Figure 5 fro coding details).
Data can only be written to the Transmit Data Register.
Transceiver control is accomplished with two Control
Registers (CRA and CRB) which occupy the same address
space. A write operation to CRB can be executed by
setting the appropriate bit in CRA. The following write
operation to the same address will then be directed to
CRB and subsequent write cycles will then be directed
back to CRA. Internal reset circuitry will clear the control
registers on power-up; however, as a precautionary
measure the initialization software should include a
routine to clear the registers. Refer to Table 5 and 6 for
details concerning the Control Registers. The IRQ/CP
pin can be programmed such that it will provide and
interrupt request signal upon validation of DTMF signals,
or when the transmitter is ready for more data (Burst
mode only). The IRQ/CP pin is configured as an open-
drain output device and as such requires a pull-up resistor
(See Figure 9).
Table 5. Control Regsiter A Description
Bit
bo
b1
b2
b3
Name
TOUT
CP/DTMF
IRQ
RSEL
CONTROL REGISTER A DESCRIPTION
Function
Description
Tone Output
Mode Control
Interrupt Enable
Register
A logic '1' enables the Tone Output. This function can be implemented in either
the Burst Mode or Non-Burst Mode.
In DTMF (logic '0'), the device is capable of generating and receiving Dual Tone
Multi-Frequency signals. When the CP (Call Progress) mode is selected (logic '1'),
a 6th order bandpass filter is enabled to allow Call Progress tones to be detected.
Call Progress tones which are within the specified bandwidth will be presented at
the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled
(B2=1). Also when the CP mode and Bust Mode have both been selected, the
transmitter will issue DTMF signal with a burst and pause of 102 mS (typ)
duration. This signal duration is twice that obtained from the DTMF transmitter, if
DTMF mode had been selected. Note that signals connot be decoded when the
CP mode of operation has been selected.
A logic '1' enables the Interrupt Mode. When this mode is active and the DTMF
Mode has been selected (b1=0), the IRQ/CP pin will pull to a logic '0' condition
when either 1) a valid DTMF signal has been received and has been present for
the guard time duration or 2) the transmitter is ready for more data (Burst Mode
only).
A logic '1' selects Control Register B on the next write cycle to the Control
Register address. Subsequent write cycles to the Control Register are directed
back to Control Register A.
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