CM8888 Datasheet, PDF (13/13 Pages) California Micro Devices Corp – CMOS INTEGRATED DTMF TRANCEIVER

CALIFORNIA MICRO DEVICES
CM8888/8888-2
Table 7. Status Register Description
Bit
Name
bo
IRQ
b1
Transmit Data Register
b2
Receive Data Register Full
b3
Delayed Steering
Status Flag Set
Interrupt has occured. Bit one
(b1) and/or bit two (b2) is set.
Pause duration has terminated
and transmitter is ready for
new data.
Valid data is in the Receive
Data Register.
Set upon the valid detection of
the absence of a DTMF signal.
Status Flag Cleared
Interrupt is inactive. Cleared after
Status Register is read.
Cleared after Status Register is read
or when in Non-Burst Mode.
Cleared after Status Register is
read.
Cleared upon the detection of a
valid DTMF signal.
Pin Function Table
Name
Description
N+ Non-inverting op-amp input.
IN- Inverting op-amp input
GS
Gain Select. Gives access to output of
front end differential amplifier for
connection of feedback resistor.
V_REF References voltage output. Nominally
V_DD /2 is used to bais inputs at inputs at
mid-rail (see application circuit).
V_SS
OSC1
Negative power supply input.
DTMF clock/oscillator input.
OSC2
Clock output. A 3.5795 MHz crystal
connected between OSC1 AND OSC2
completes the internal oscillator circuit.
TONE Dual tone Multi-Frequency (DTMF)
output.
WR Write input. A low on this pin when
CS is low enables data transfer from
the microprocessor. TTL compatible.
CS
Chip Select. TTl input. (CS =0 to
select the chip).
RSO Register select input. See register
decode table. TTL compatible.
RD Read input. A low on this pin when
CS is low enables data transfer to the
microprocessor. TTL compatible.
Name
Description
IRQ/CP
Interupt request to microprocessor
(open-drain output). Also, when
Call Progress (CP) Mode has been
selected and Interrupt enabled the
IRQ/CP pin will output a rectangular
wave signal representative of the
input siganl applied at the input op-
amp. The input signal must be
within the bandwidth limits of the
Call Progress filter. See Filter 6.
DO-D3 Microprocessor data bus. TTL
compatible.
ESt Early Spring output. Presents a
logic high once the digital algorithm
has detected a valid tone pair (signal
condition). Any momentary loss of signal
condition will cause EST to
return to a logic low.
StGT
Steering input/Guard Time output
(bidierectional). A voltage greater
than VTS, detected at St causes the
device to register the detected tone
pair and update the output latch. A
voltage less than VTS, frees the device
to accept a new tone pair. The GT output
acts to reset the external steering time-
constant; its state is a function of ESt and
the voltage on St.
V_DD
Positive power supply input.
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