CM2030 Datasheet, PDF (6/14 Pages) California Micro Devices Corp – HDMI Transmitter Port Protection and Interface Device

CM2030
to ten (10) CEC devices may reside on the bus, and
they may be daisy chained out through other physical
connectors including other HDMI ports or other dedi­
cated CEC links. The high level protocol of CEC can be
implemented in a simple microcontroller or other inter­
face with any I/OD (input/open-drain) GPIO.
levels and HDMI slew-rate and isolation specifications
(See Figure 5).
CEC
CEC
RX
I/OD
GPIO
TX
CEC I/F
μP
CM2030
Figure 3. Typical μC I/OD Driver
To limit possible EMI and ringing in this potentially
complex connection topology, the rise- and fall-time of
this line are limited by the specification. However,
meeting the slew-rate limiting requirements with addi­
tional discrete circuitry in this bi-directional block is not
trivial without an additional RX/TX control line to limit
the output slew-rate without affecting the input sensing
(See Figure 4).
Figure 5. Integrated CM2030 Solution
The CM2030 also includes an internal backdrive pro­
tected static pullup 120μA current source from the
CE_SUPPLY rail in addition to the dynamic slew rate
control circuitry.
Figure 6 shows a typical shaped CM2030 CEC output
(bottom) against a ringing uncontrolled discrete solu­
tion (top).
RX
TX
TX_EN
CEC
Slew Rate
Limited
3-State Buffer
Figure 4. Three-Pin External Buffer Control
Simple CMOS buffers cannot be used in this applica­
tion since the load can vary so much (total pullup of
27kΩ to less than 2kΩ, and up to 7.3nF total capaci­
tance.) The CM2030 targets an output drive slew-rate
of less than 100mV/μs regardless of static load for the
CEC line. Additionally, the same internal circuitry will
perform active termination, thus reducing ringing and
overshoot in entertainment systems connected to leg­
acy or poorly designed CEC nodes.
The CM2030’s bi-directional slew rate limiting is inte­
grated into the CEC level-shifter functionality thus
allowing the designer to directly interface a simple low
voltage CMOS GPIO directly to the CEC bus and
simultaneously guarantee meeting all CEC output logic
Figure 6. CM2030 CEC Output
© 2007 California Micro Devices Corp. All rights reserved.
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Issue A – 11/16/07