PACVGA201 Datasheet, PDF (3/3 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

CALIFORNIA MICRO DEVICES
Typical Connection Diagram
PACVGA201
A resistor may be necessary between the V_CC2 pin and ground if protection against a stream of ESD pulses is required
while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such that the extra
charge deposited into the V_CC2 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs.
The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA201
is in the power-up state, an internal discharge resistor is connected to ground via a FET switch for this purpose.
For the same reason, V_CC1 and V_CC3 may also require bypass capacitor discharging resistors to ground if there are no
other components in the system to provide a discharge path to ground.
STANDARD PART ORDERING INFORMATION
Package
Ordering Part Number
Pins
Style
Part Marking
16
QSOP
PACVGA201Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
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215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com
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