PACVGA201 Datasheet, PDF (1/3 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

CALIFORNIA MICRO DEVICES
VGA PORT COMPANION CIRCUIT
Features
• 7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
• Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
• TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
• Three power supplies for design flexibility
• Compact 16-pin QSOP package
Pin Diagram
PACVGA201
16-PIN QSOP PACKAGE
Product Description
The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low
voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.
An internal diode (D1, in schematic below) is provided such that V_CC2 is derived from V_CC3. (V_CC2 does not require an external
power supply input.) In applications where V_CC3 may be powered down, diode D1 blocks any DC current path from the
DDC_OUT pins back to the powered down V_CC3 rail via the upper ESD protection diodes.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V_CC3.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the V_CC3 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved. PAC VGA201™ is a trademark of California Micro Devices Corp.
4/00
215 Topaz Street, Milpitas, California 95035 Tel: [phone]
Fax: [phone]
www.calmicro.com
C0651299
1