CM3131 Datasheet, PDF (3/10 Pages) California Micro Devices Corp – Triple Linear Voltage Regulator for DDR-I/-II Memory

CM3131
Functional Description
The CM3131-01 / -11 and CM3131-02 provide
power for DDR-I/DDR-II memories from three
voltage regulators on-chip with either one or two
external N-FETs respectively. There is an over-
temperature thermal shutdown if any of the
regulators overheat. Each regulator has reverse
current protection in the event of any being shut
down.
The linear regulator-driver/s with external N-FET/s
can provide up to 15A at 2.5V/1.8V for the V_DDQ of
DDR-I/-II memory, from an input supply voltage of
2.8V-3.6V. An external feedback resistor divider,
connected to the SENSE1 pin, enables selection of
V_DDQ output voltages from 2.2V to 2.8V for use with
DDR-I memories requiring other than 2.5V for V_DDQ.
V_DDQ = 1.25V x (R1+R2)/R2. When SENSE1 is
connected to GND or left open, V_DDQ is fixed at
2.50V (and VTT at 1.25V). For DDR-II operation,
V_DDQ can be set from 1.7V to 1.9V.
The V_TT regulator is a linear source-sink regulator
powered from the V_DDQ output that supplies the V_TT
supply required by DDR-I memory termination
resistors. This regulator sinks or sources up to 2A at
1.25V to or from the DDR-I bus termination resistors.
For DDR-II applications, the regulator sinks or
sources 0.65A at 0.9V. The V_TT output voltage
accurately tracks V_DDQ/2 to 1%. When there is no
V_CC provided, V_TT is powered down and its output is
0V. This regulator has overload current limiting of
2.5A.
The standby regulator is a LDO regulator that is
powered from a standby voltage, V_STBY, of 3.3V or
5V, and supplies a regulated output of up to 500mA
to the V_DDQ of the DDR memory to enable it to retain
its contents during the standby mode. It provides
2.5V for DDR-I and 1.8V for DDR-II.
The CM3131-01 and CM3131-11 differ with regards
the selection of truth table for determining which S0-
S5 sequencing matrix the chip is set for. The
CM3131-02 has both EN and SEL pins to more
accurately define each Sx stage without monitoring
the V_CC or V_STBY voltages.
Two CM3131s can be ganged together to provide
V_DDQ power to dual channels of DDR memory, and
the memory controller chip of any chip set.
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V_CC
PSOP-8
CM3131-01/11
V_DDQ
LDO Drive _DRIVE
FET
Internal V_SBY voltage
doubler ensures V_G > 5.3V
Drives any N-FET with C_GS
<1200pF
5V_STBY / 3.3V_STBY
SEL / EN
C_SBY
C_CC
V_DDQ
LDO
V_DDQ
V_DDQ / V_TT
Control
R1
SENSE
V_DDQ
Linear
Source-Sink
V_TT Reg
R2
GND
V_TT
GND
C_TT
V_DDQ
C_DDQ
V_TT
Only needed for
DDR-I if V_DDQ is
not 2.5V, e.g. 2.6V
or 2.7V.
Set to 1.7V to
1.9V for DDR-II
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V_CC
CM3131-02
V_DDQ
LDO Drives
DRIVE1
DRIVE2
N-FET1
5V_STBY / 3.3V_STBY
SEL
EN
C_SBY
C_CC
V_DDQ
LDOs
V_DDQ1
V_DDQ2
V_DDQ / V_TT
Control
R1
R3
SENSE1
C_DDQ2
SENSE2
V_DDQ
R2
R4
Linear
Source-Sink
V_TT Reg
V_TT
GND
GND
C_TT
N-FET2
V_DDQ1
V_DDQ2
C_DDQ1
V_TT
Examples of Single and Dual N-FET Drive Configurations
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: [phone] Fax: [phone]
www.calmicro.com
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