CS4373 Datasheet, PDF (7/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

CS4373
SWITCHING CHARACTERISTICS
Parameter
Symbol Min
Typ
Max Unit
MCLK Frequency
(Note 14)
Normal Power Mode
f_c
Low Power Mode
-
2.048
-
MHz
-
1.024
-
MHz
MCLK Duty Cycle
DC_CLK
40
MCLK Jitter (In-band or aliased in-band)
CKJ_IB
-
MCLK Jitter (Out-of-band)
CKJ_OB
-
Rise Times:
Any Digital Input
t_rise
-
Fall Times:
Any Digital Input
t_fall
-
SYNC Setup Time to MCLK falling
(Note 15) t_mss
20
SYNC Hold Time after MCLK falling
t_msh
20
-
60
%
-
300
ps
-
1
ns
-
50
ns
-
50
ns
-
-
ns
-
-
ns
Notes: 14. If MCLK is removed, the CS4373 enters a sleep mode state.
15. SYNC latched on MCLK falling edge, data output on next MCLK rising edge.
t _rise
t _fall
Figure 1. Rise and Fall Times
0.9*VD
0.1*VD
MCLK
(2.048 MHz)
MSYNC
TDATA
(256 kHz)
t0
t_mss
t_mclk
t_msync
t_msh
t_tdat
Figure 2. Timing
DS577F1
7