CS4373 Datasheet, PDF (10/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

CS4373
3. GENERAL DESCRIPTION
The CS4373 DAC is designed to fully verify the
performance of the acquisition channel. Also,
the input switching arrangements allows for
verification of sensor source impedance and,
in the case a moving-coil geophone, basic pa-
rameters of the electro-mechanical transfer
function.
Test signals are typically generated by the
CS5376A or CS5378 digital filter. The
CS5376A/78 supplies TDATA with a ∆Σ bit-
stream at a rate of MCLK/8. The DAC recon-
structs the digital bitstream to analog.
The full scale output voltage of the DAC
matches the maximum input signal rating of
the CS3301 and the CS3302 amplifier. A pas-
sive, programmable attenuator provides out-
put levels that matches all gain settings of
CS3301 and CS3302 while preserving the S/N
of the DAC.
The DAC can be operated at full scale for sig-
nal frequencies up to 200 Hz. For frequencies
above 200 Hz the amplitude must be reduced
to -20 dB with respect to full scale.
4. ANALOG OUTPUTS
4.1 CAP+ / CAP-
The CS4373 DAC needs an anti-alias filter to
function properly. The filter is constructed with
resistors internal to the CS4373 and a capaci-
tor connected the CAP+ and CAP- pins. This
filter will eliminate out of band signals from the
OUT± and BUF± outputs.
A 10 nF COG capacitor is required across
CAP±; other types of capacitors, such as X7R,
do not have the stability required. Using the
10 nF COG sets the -3 dB corner of the output
anti-alias filter to 40 kHz.
4.2 OUT+ / OUT-
The OUT± pins are high precision, high output
impedance differential outputs designed to
test external electronics within the chip set.
These outputs directly interface to the CS3301
and CS3302 for multiple test modes (See
Figure 4 on page 8 for typical connection).
These outputs can be attenuated to match the
gain ranges of the CS3301/3302 using ATT0,
ATT1, and ATT2.
4.3 BUF+ / BUF-
BUF± are buffered differential outputs used to
test external sensors such as hydrophones or
geophones. These outputs are also attenuat-
ed internally with the ATT0, ATT1 and ATT2
pins to match the gain ranges of the CS3301
and CS3302 (See Figure 4 on page 8 for typi-
cal connection).
5. DIGITAL FILTER INTERFACE
The CS4373 is designed to operate with the
CS5376A or CS5378 digital filter. The
CS5376A/78 generates the master clock
(MCLK), the ∆Σ test bitstream (TDATA) and
the synchronization signal input (SYNC). Each
of these can be configured within the digital fil-
ter to fit the application requirements.
5.1 Signal Bitstream Input - TDATA
TDATA is the test bitstream input for the
CS4373. It is a ∆Σ one’s density bitstream in-
put at a rate of MCLK/8. The digital filter has a
bitstream available on its TBSDATA pin. When
used with the CS5376A/78, TDATA can be
connected directly to TBSDATA for it’s bit-
stream generation.
5.2 Master Clock - MCLK
For proper operation, the CS4373 must be
provided with a CMOS compatible clock on the
MCLK pin. MCLK must have less than 300 ps
of in-band jitter to maintain full performance
specifications.
When used with the CS5376A/78 digital filters,
MCLK is automatically generated and is typi-
cally 2.048 MHz or 1.024 MHz.
10
DS577F1