CS4373 Datasheet, PDF (15/20 Pages) Cirrus Logic – Low-power, High-performance Delta-Sigma Test DAC

CS4373
8. ATTENUATION SETTINGS
The DAC outputs can be attenuated to match
the gain ranges of the CS3301 and CS3302
amplifiers. Using pins ATT0, ATT1 and ATT2,
the outputs of the DAC can be set to one of
7 attenuation options. Table 2 shows each at-
tenuation option.
Attenuation
Selection
1
1/2
1/4
1/8
1/16
1/32
1/64
Reserved
ATT2
0
0
0
0
1
1
1
1
ATT1
0
0
1
1
0
0
1
1
Table 2. Attenuator Selection
ATT0
0
1
0
1
0
1
0
1
9. POWER MODES
Five power modes are available when using
the CS4373. Normal, low power modes are
operational modes; power down and sleep
mode are non-operational standby modes.
9.1 Normal Power Mode
The normal operational mode for the CS4373,
LPWR=0 and MCLK=2.048 MHz, provides the
best performance with low power consump-
tion. This power mode is recommended when
maximum performance is required.
9.2 Low Power Mode
The CS4373 has a low-power operational
mode, LPWR = 1 and MCLK = 1.024 MHz,
that reduces power consumption at the ex-
pense of 3 dB SNR. This operational mode is
recommended when minimizing power is more
important than maximizing SNR.
9.3 Sleep Mode
When selecting Test Mode 7, the CS4373 will
be put in a sleep mode in which the DAC is in-
active. Each analog output is placed into a
high impedance state.
9.4 Power Down
The CS4373 is automatically placed into pow-
er down if MCLK is disabled. It is equipped
with loss of clock detection circuitry to force
power down if MCLK is removed. In power
down the DAC is inactive and the analog out-
puts are placed in a high impedance state.
When used with the CS5376A or CS5378 the
CS4373 will be in this state upon power-up
since MCLK is disabled by default.
10. POWER SUPPLY
The CS4373 has one positive analog power
supply pin, VA+, one negative analog power
supply pin, VA-, one digital power supply pin,
VD, and one digital ground pin, DGND. The
analog and digital circuitry are separated inter-
nally to enhance performance, therefore pow-
er must be supplied to all three supply pins.
The digital ground pin must be connected to
system ground.
When used with the CS5376A or CS5378 dig-
ital filter the maximum voltage differential be-
tween the CS4373 digital supply, VD, and the
I/O supplies, (VDD1, VDD2, VDDPAD) must
be 0.3 V or less.
10.1 Power Supply Bypassing
The analog supply pins, VA+, VA-, should be
decoupled to system ground with a 0.1 µF ca-
pacitor; while the digital supply pin, VD, should
be decoupled to system ground with a 0.01 µF
capacitor. Bypass capacitors can be X7R, tan-
talum, or any other dielectric types.
10.2 SCR Latch-up Considerations
The VA- pin is tied to the CS4373 CMOS sub-
strate and should always be connected to the
most negative supply voltage to ensure SCR
latch-up does not occur. In general, latch-up
may occur when any pin voltage (including the
analog inputs) is 0.7 V or more below VA-, or
7.6 V or more above VA-.
DS577F1
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