CS4220 Datasheet, PDF (7/32 Pages) Cirrus Logic – 24-Bit Stereo Audio Codec with 3V Interface

CS4220 CS4221
SWITCHING CHARACTERISTICS (T_A = 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with
30 pF)
Parameter
Audio ADC’s and DAC’s Sample Rate
XTI Frequency
XTI = 256, 384, or 512 Fs
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Jitter Tolerance
RST Low Time
(Note 10)
SCLK falling edge to SDOUT output valid
DSCK = 0
LRCK edge to MSB valid
SDIN setup time before SCLK rising edge
DSCK = 0
SDIN hold time after SCLK rising edge
DSCK = 0
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK edge
DSCK = 0
LRCK edge to SCLK rising
DSCK = 0
Symbol
Fs
t_dpd
t_lrpd
t_ds
t_dh
t_sckw
t_sckh
t_sckl
t_lrckd
t_lrcks
Min
4
1.024
13
21
31
13
21
31
-
10
-
-
25
25
(---1---2---8-1---)---F----s-
40
40
35
40
Typ
Max Unit
-
50
kHz
-
26
MHz
-
-
ns
-
-
-
-
-
-
ns
-
-
-
-
500
- psRMS
-
-
ms
-
(---3---8---4-1---)---F----s- ^{+ 20}
ns
-
45
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
Notes: 10. After powering up the CS4220/1, PDN should be held low for 10 ms to allow the power supply to settle.
LRCK
SCLK*
SDIN
SDOUT
t _lrckd
t _lrcks
t _sckh
t _sckl
t _sckw
t _{lrpd t ds}
t _dh
MSB
t _dpd
MSB-1
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
Figure 1. Serial Audio Port Data I/O Timing
DS284PP3
7