CS4220 Datasheet, PDF (22/32 Pages) Cirrus Logic – 24-Bit Stereo Audio Codec with 3V Interface

CS4220 CS4221
8. APPLICATIONS
8.1 Overview
The CS4220 is a stand-alone device controlled
through dedicated pins. The CS4221 is controlled
with an external microcontroller using the serial
control port.
8.2 Grounding and Power Supply
Decoupling
As with any high resolution converter, the
CS4220/1 requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance. Figures 4 and 5 shows the
recommended power arrangement with VA, VD
and VL connected to clean supplies. Decoupling
capacitors should be located as close to the device
package as possible. If desired, all supply pins may
be connected to the same supply, but a decoupling
capacitor should still be used on each supply pin.
8.3 High Pass Filter
The operational amplifiers in the input circuitry
driving the CS4220/1 may generate a small DC off-
set into the A/D converter. The CS4220/1 includes
a high pass filter after the decimator to remove any
DC offset which could result in recording a DC lev-
el, possibly yielding "clicks" when switching be-
tween devices in a multichannel system.
8.4 Analog Outputs
The recommended off-chip analog filter is either a
2nd order Butterworth or a 3rd order Butterworth,
if greater out-of-band noise filtering is desired. The
CS4220/1 DAC interpolation filter has been pre-
compensated for an external 2nd order Butterworth
filter with a 3 dB corner at Fs, or a 3rd order But-
terworth filter with a 3 dB corner at 0.75 Fs to pro-
vide a flat frequency response and linear phase over
the passband (see Figure 14 for Fs = 48 kHz). If the
recommended filter is not used, small frequency re-
sponse magnitude and phase errors will occur. In
addition to providing out-of-band noise attenua-
tion, the output filters shown in Figure 14 provide
differential to single-ended conversion.
8.5 Master vs. Slave Mode
The CS4220/1 may be operated in either master
mode or slave mode. In master mode, SCLK and
LRCK are outputs which are internally derived
from MCLK. The device will operate in master
mode when a 47 kΩ pulldown resistor is present on
SDOUT at startup or after reset, see Figure 5.
LRCK and SCLK are inputs to the CS4220/1 when
operating in slave mode. See Figures 8-11 for the
available clocking modes.
8.6 De-emphasis
The CS4220/1 includes digital de-emphasis for 32,
44.1, or 48 kHz sample rates. The frequency re-
sponse of the de-emphasis curve, as shown in Fig-
ure 15, will scale proportionally with changes in
samples rate, Fs. The de-emphasis feature is in-
cluded to accommodate older audio recordings that
utilize pre-emphasis as a means of noise reduction.
De-emphasis control is achieved with the DEM1/0
pins on the CS4220 or through the DEM1-0 bits in
the DSP Port Mode Byte (#5) on the CS4221.
8.7 Power-up / Reset / Power Down
Calibration
Upon power up, the user should hold RST = 0 for
approximately 10 ms. In this state, the control port
is reset to its default settings and the part remains in
the power down mode. At the end of RST, the de-
vice performs an offset calibration which lasts ap-
proximately 50 ms after which the device enters
normal operation. In the CS4221, a calibration may
also be initiated via the CAL bit in the ADC Con-
trol Byte (#1). The CALP bit in the ADC Control
Byte is a read only bit indicating the status of the
calibration.
Reset/Power Down is achieved by lowering the
RST pin causing the part to enter power down.
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