CS4220 Datasheet, PDF (2/32 Pages) Cirrus Logic – 24-Bit Stereo Audio Codec with 3V Interface

CS4220 CS4221
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ANALOG CHARACTERISTICS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS .......................................................................................... 6
RECOMMENDED OPERATING CONDITIONS ...................................................................... 6
SWITCHING CHARACTERISTICS ......................................................................................... 7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) .................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE (CS4221) ..................... 9
2. TYPICAL CONNECTION DIAGRAM — CS4220 ................................................................... 10
3. TYPICAL CONNECTION DIAGRAM — CS4221 ................................................................... 11
4. REGISTER QUICK REFERENCE - CS4221 .......................................................................... 12
5. REGISTER DESCRIPTIONS - CS4221 .................................................................................. 13
5.1 ADC Control (address 01h) .............................................................................................. 13
5.1.1 Power Down ADC (PDN) ....................................................................................... 13
5.1.2 Left and Right channel High Pass Filter Defeat (HPDR-HPDL) ............................. 13
5.1.3 Left and Right Channel ADC Muting (ADMR-ADML) ............................................. 13
5.1.4 Calibration Control (CAL) ....................................................................................... 13
5.1.5 Calibration Status (CALP) (Read Only) .................................................................. 13
5.1.6 Clocking Error (CLKE) (Read Only) ....................................................................... 14
5.2 DAC Control (address 02h) .............................................................................................. 14
5.2.1 Mute on Consecutive Zeros (MUTC) ...................................................................... 14
5.2.2 Mute Control (MUTR-MUTL) .................................................................................. 14
5.2.3 Soft RAMP Control (SOFT) .................................................................................... 14
5.2.4 Soft RAMP Step Rate (RMP) ................................................................................. 15
5.3 Left Channel Output Attenuator Level (address 03h) ...................................................... 15
5.4 Right Channel Output Attenuator Level (address 04h) ................................................... 15
5.4.1 Attenuation level (ATT7-ATT0) ............................................................................... 15
5.5 DSP Port Mode (address 05h) ......................................................................................... 16
5.5.1 De-emphasis Control (DEM) .................................................................................. 16
5.5.2 Serial Input/Output Data SCLK Polarity Select (DSCK) ......................................... 16
5.5.3 Serial Data Output Format (DOF) .......................................................................... 16
5.5.4 Serial Data Input Format (DIF) ............................................................................... 16
5.6 Converter Status Report (Read Only) (address 06h) ....................................................... 17
5.6.1 Left and Right Channel Acceptance Bit (ACCR-ACCL) ......................................... 17
5.6.2 Left and Right Channel ADC Output Level (LVR and LVL) .................................... 17
5.7 Master Clock Control (address 07h) ................................................................................ 17
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