BUF12800 Datasheet, PDF (7/20 Pages) Burr-Brown (TI) – REFERENCE VOLTAGE GENERATOR for LCD GAMMA CORRECTION

BUF12800
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READ/WRITE OPERATIONS
The BUF12800 is able to read from a single DAC or
multiple DACs, or write to the register of a single DAC, or
multiple DACs in a single communication transaction.
DAC addresses begin with 0000, which corresponds to
DAC_A, through 1011, which corresponds to DAC_L.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.
Writing
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D4 are unused
and should be set to 0. Bits D3−D0 are the DAC
address. Only DAC addresses 0000 to 1011 are valid
and will be acknowledged.
4. Send two bytes of data for the specified DAC. Begin
by sending the most significant byte first (bits D15−D8,
of which only bits D9 and D8 are used), followed by the
least significant byte (bits D7−D0). The DAC register
is updated after receiving the second byte.
5. Send a STOP condition on the bus.
The BUF12800 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage. See the
Output Latch section.
The process of updating multiple registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master will continue to send data
for the next register. The BUF12800 will automatically and
sequentially step through subsequent registers as addi-
tional data is sent. The process will continue until all de-
sired registers have been updated or a stop condition is
sent.
To write to all registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send either the DAC_A address byte to start at the
first DAC or send the address of whichever DAC will
be the first to be updated. The BUF12800 will begin
with this DAC and step through subsequent DACs in
sequential order.
4. Send 24 bytes of data. The first two bytes are for
DAC_A. It is automatically updated after receiving the
second byte. The next two are for DAC_B. The DAC
register is updated after receiving the fourth byte. The
last two bytes are for DAC_L. The DAC register is
updated after receiving the 24th byte. For each DAC,
SBOS315 − DECEMBER 2004
begin by sending the most significant byte (bits
D15−D8, of which only bits D9 and D8 have meaning),
followed by the least significant byte (bits D7−D0).
5. Send a STOP condition on the bus.
The BUF12800 will acknowledge each byte. To terminate
communication, send a Stop or Start condition on the bus.
Only DACs that have received both bytes will be updated.
Reading
To read the registers of one DAC:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D4 have no
meaning; Bits D3−D0 are the DAC address. Only DAC
addresses 0000 to 1011 are valid and will be
acknowledged.
4. Send a START or STOP/START condition on the bus.
5. Send correct device address and read/write
bit = HIGH. The BUF12800 will acknowledge this
byte.
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, of which only bits D9 and D8 have
meaning); the next is the least significant byte (bits
D7−D0).
7. Acknowledge after receiving each byte.
8. Send a STOP condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
To read all DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send the DAC_A address byte to start at the first DAC.
4. Send the device address and read/write bit = HIGH.
5. Receive 24 bytes of data. The first two bytes are for
DAC_A. The next two are for DAC_B. The last two
bytes are for DAC_L. For each DAC, the first received
byte is the most significant byte (bits D15−D8, of
which only bits D9 and D8 have meaning). The next
byte is the least significant byte (bits D7−D0).
6. Acknowledge after receiving each byte.
7. Send a STOP condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
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