CS4218 Datasheet, PDF (5/44 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4218
SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input
Levels: Logic 0 = 0V, Logic 1 = VD)
Parameter
Symbol Min
Typ
Max Units
Input clock (CLKIN) frequency
SM3 Multiplier Mode CLKIN 64
768
800
SM3 Master and Slave Modes, SM4, SM5 CLKIN 1.024 12.288 12.8
KHz
MHz
CLKIN low time
tckl
15
-
-
ns
CLKIN high time
tckh
15
-
-
ns
Sample Rate
(Note 1) Fs
4
-
50
kHz
DI pins setup time to SCLK edge
(Note 1) ts2
10
-
-
ns
DI pins hold time from SCLK edge
(Note 1) th2
8
-
-
ns
DO pins delay from SCLK edge
tpd2
-
-
30
ns
SCLK and SSYNC output
delay from CLKIN rising
All master Modes (Note 1) tpd3
-
-
50
ns
SCLK period
All master Modes (Notes 1,7) tsckw
- 1/(Fs*bpf) -
s
Slave Mode
75
-
-
ns
SCLK high time
Slave Mode tsckh
30
-
-
ns
SCLK low time
Slave Mode tsckl
30
-
-
ns
SDIN, SSYNC setup time to SCLK edge
Slave Mode ts1
15
-
-
ns
SDIN, SSYNC hold time from SCLK edge
Slave Mode th1
10
-
-
ns
SDOUT delay from SCLK edge
tpd1
-
-
28
ns
Output to Hi-Z state
bit 64 (Note 1) thz
-
-
12
ns
Output to non-Hi-Z
bit 1 (Note 1) tnz
15
-
-
ns
RESET pulse width low
500
-
-
ns
CCS low to CCLK rising
CDIN setup to CCLK falling
CCLK low to CDIN invalid (hold time)
CCLK high time
CCLK low time
CCLK Period
CCLK rising to CDOUT data valid
CCLK rising to CDOUT Hi-Z
CCLK falling to CCS high
RESET low time prior to PDN rising
SM4 (Note 1) tcslcc
25
-
SM4 (Note 1) tdiscc
15
-
SM4 (Note 1) tccdih
10
-
SM4 (Note 1) tcclhh
25
-
SM4 (Note 1) tcclhl
25
-
SM4 (Note 1) tcclkw
75
-
SM4 (Note 1) tccdov
-
-
SM4 (Note 1) tccdot
-
-
SM4 (Note 1) tcccsh
0
-
trph
100
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
30
ns
30
ns
-
ns
-
ns
RESET low hold time after PDN rising
trhold
50
-
-
ms
Notes: 7. When the CS4218 is in master modes (SSYNC and SCLK outputs), the SCLK duty cycle is 50%.
The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
DS135F1
5