CS4218 Datasheet, PDF (31/44 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4218
AGND - Analog Ground, PIN 23(L), 17(Q).
Analog ground. Must be connected to DGND with zero impedance.
Analog Inputs
RIN1 - Right Input #1, PIN 25(L), 19(Q).
Right analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF.
RIN2 - Right Input #2, PIN 26(L), 20(Q).
Right analog input #2. Full scale input, with no gain, is 1Vrms, centered at REFBUF.
LIN1 - Left Input #1, PIN 27(L), 21(Q).
Left analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF.
LIN2 - Left Input #2, PIN 28(L), 22(Q).
Left analog input #2. Full scale input, with no gain, is 1Vrms, centered at REFBUF.
Analog Outputs
ROUT - Right Channel Output, PIN 15(L), 9(Q).
Right channel analog output. Maximum signal is 1 Vrms centered at REFBUF.
LOUT - Left Channel Output, PIN 16(L), 10(Q).
Left channel analog output. Maximum signal is 1 Vrms centered at REFBUF.
REFBYP - Analog Reference Decoupling, PIN 21(L), 15(Q).
A 10 µF and 0.1 µF capacitor must be attached between REFBYP and REFGND.
REFGND - Analog Reference Ground Connection, PIN 22(L), 16(Q).
Connect to AGND.
REFBUF - Buffered Reference Out, PIN 20(L), 14(Q).
A nominal +2.1V output for setting the bias level for external analog circuits.
Serial Digital Audio Interface Signals
SDIN - Serial Port Data In, PIN 42(L), 36(Q).
Digital audio data to the DACs and level control information is received by the CS4218 via
SDIN.
SDOUT - Serial Port Data Out, PIN 43(L), 37(Q).
Digital audio data from the ADCs and status information is output from the CS4218 via
SDOUT.
SCLK - Serial Port Bit Clock, PIN 44(L), 38(Q).
SCLK controls the digital audio data on SDOUT and latches the data on SDIN. SCLK must be
synchronous to the master clock.
DS135F1
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