CS4218 Datasheet, PDF (16/44 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4218
SCLK must be generated externally. When the
codec is the serial port master, the serial port sig-
nal transitions are controlled with respect to the
internal analog sampling clock to minimize the
amount of digital noise coupled into the analog
section. Since SSYNC and SCLK are externally
derived when the codec slaves to the serial port,
optimum noise management cannot be obtained;
therefore, master modes should be used when-
ever possible. Multiplier sub-modes are identical
to the SM3 modes except the master clock,
CLKIN, is internally multiplied by 16. A
0.47 µF capacitor must be tied to the FILT pin
when using the Multiplier sub-modes.
Master Clock Frequency
In SM3-M and SM3-S sub-modes, the master
clock, CLKIN, must be 256 × Fs_max. For exam-
ple, given a 48 kHz maximum sample frequency,
the master clock frequency must be
12.288 MHz. In SM3-MM and SM3-MS sub-
mo des, CLKIN must be 16xFs_max. For
example, given a 48 kHz maximum sample fre-
quency, the master clock frequency must be
768 kHz. SCLK and SSYNC must be synchro-
nous to the master clock.
Word A
S_Su_ub_b--_ff_rr_aa_mm_e e
Word B
DAC - Left Word
00000
DAC - Right Word
00
00
Figure 11. Serial Data Input Format - SM3, SM5.
Word A
S_Su_ubb_--_frf_ara_mm_e e
Word B
ADC - Left Word
16
00000
ADC - Right Word
000000010000
X
Figure 12. Serial Data Output Format - SM3, SM5.
DS135F1