CS42448 Datasheet, PDF (46/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

6.4 FUNCTIONAL MODE (ADDRESS 03H)
7
DAC_FM1
6
DAC_FM0
5
ADC_FM1
4
ADC_FM0
3
MFreq2
2
MFreq1
1
MFreq0
0
Reserved
6.4.1 DAC FUNCTIONAL MODE (DAC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the DAC serial port.
6.4.2 ADC FUNCTIONAL MODE (ADC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the ADC serial port.
6.4.3 MCLK FREQUENCY (MFREQ[2:0])
Default = 000
Function:
Sets the appropriate frequency for the supplied MCLK. For TDM and OLM #2 operation,
ADC/DAC_SCLK must equal 256Fs. For OLM #1 operation, ADC/DAC_SCLK must equal 128Fs.
MCLK can be equal to or greater than the higher frequency of ADC_SCLK or DAC_SCLK.
Ratio (xFs)
MFreq2
0
0
0
0
1
MFreq1
0
0
1
1
X
MFreq0
Description
0 1.0290 MHz to 12.8000 MHz
1 1.5360 MHz to 19.2000 MHz
0 2.0480 MHz to 25.6000 MHz
1 3.0720 MHz to 38.4000 MHz
X 4.0960 MHz to 51.2000 MHz
SSM
256
384
512
768
1024
DSM
128
192
256
384
512
QSM
64
96
128
192
256
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats
46
DS648PP2