CS42448 Datasheet, PDF (32/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

4.4 System Clocking
The CODEC (ADC & DAC) serial audio interface ports operate both as a slave or master. The serial ports
accept externally generated clocks in slave mode and will generate synchronous clocks derived from an
input master clock in master mode. In the TDM format the ADC and DAC serial ports will only operate as
a slave. In OLM #2 the serial ports will accept or output a 256Fs SCLK. See the registers “DAC Functional
Mode (DAC_FM[1:0])” on page 46 and “ADC Functional Mode (ADC_FM[1:0])” on page 46 for setting up
master/slave mode.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must
be an integer multiple of, and synchronous with, the system sample rate, Fs.
The required integer ratios, along with some common frequencies, are illustrated in tables 2 to 4. The fre-
quency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFreq[2:0])” on page 46.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 2. Single-Speed Mode Common Frequencies
1024x
32.7680
45.1584
49.1520
Sample Rate
(kHz)
64
88.2
96
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
MCLK (MHz)
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
Table 3. Double-Speed Mode Common Frequencies
512x
32.7680
45.1584
49.1520
Sample Rate
(kHz)
176.4
192
64x
11.2896
12.2880
96x
16.9344
18.4320
MCLK (MHz)
128x
22.5792
24.5760
Table 4. Quad-Speed Mode Common Frequencies
192x
33.8688
36.8640
256x
45.1584
49.1520
4.5 CODEC Digital Interface Formats
The ADC and DAC serial ports support the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and
TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 15-20. Data is
clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. The
serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronously derived from the master clock and
be equal to 256x, 128x, 64x, 48x or 32x Fs depending on the interface format selected and desired speed
mode. One Line Mode #1 and One Line Mode #2 will operate in master or slave mode. Refer to Table 5
for required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 - 8.
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