CS42428 Datasheet, PDF (46/67 Pages) Cirrus Logic – 114 dB, 192kHz 8-Ch CODEC WITH PLL

CS42428
5.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)
Default = 00
00 - Reserved
01 - De-Emphasis for 32 kHz sample rate.
10 - De-Emphasis for 44.1 kHz sample rate.
11 - De-Emphasis for 48 kHz sample rate.
Function:
Used to specify which de-emphasis filter to apply when the FORCE PLL LOCK (FRC_PLL_LK) in
reg06h is enabled.
5.17.3 INTERRUPT PIN CONTROL (INTX)
Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the interrupt pin (INT) will indicate an interrupt condition.
5.18 Interrupt Status (address 20h) (Read Only)
7
UNLOCK
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
OverFlow
0
Reserved
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always
be “0” in this register.
5.18.1 PLL UNLOCK (UNLOCK)
Default = 0
Function:
PLL unlock status bit. This bit will go high if the PLL becomes unlocked.
5.18.2 ADC OVERFLOW (OVERFLOW)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42428 ADC signal path.
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