CS42428 Datasheet, PDF (32/67 Pages) Cirrus Logic – 114 dB, 192kHz 8-Ch CODEC WITH PLL

CS42428
5 REGISTER DESCRIPTION
All registers are read/write except for I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock
Status and Interrupt Status Register which are read only. See the following bit definition tables for bit as-
signment information. The default state of each bit after a power-up sequence or reset is listed in each bit
description.
5.1 Memory Address Pointer (MAP)
Not a register
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
5.1.1 INCREMENT(INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
5.1.2 MEMORY ADDRESS POINTER (MAPX)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control
port.
5.2 Chip I.D. and Revision Register (address 01h) (Read Only)
7
Chip_ID3
6
Chip_ID2
5
Chip_ID1
4
CHIP_ID0
3
Rev_ID3
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
5.2.1 CHIP I.D. (CHIP_IDX)
Default = 1110
Function:
I.D. code for the CS42428. Permanently set to 1110.
5.2.2 CHIP REVISION (REV_IDX)
Default = 0001
Function:
CS42428 revision level. Revision C is coded as 0011.
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