CS42428 Datasheet, PDF (10/67 Pages) Cirrus Logic – 114 dB, 192kHz 8-Ch CODEC WITH PLL

CS42428
3 APPLICATIONS
3.1 Overview
The CS42428 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital con-
verters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters
(DAC). Other functions integrated within the codec include independent digital volume controls for each
DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters,
and an on-chip voltage reference. All serial data is transmitted through one configurable serial audio inter-
face for the ADC with enhanced one line modes of operation allowing up to 6 channels of serial audio data
on one data line. All functions are configured through a serial control port operable in SPI mode or in I²C
mode. Figure 1 shows the recommended connections for the CS42428.
The CS42428 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register “Functional Mode (address 03h)” on page 33. Single-Speed mode
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.
Using the integrated PLL, a low jitter clock is recovered from the ADC LRCK input signal. The recovered
clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.
3.2 Analog Inputs
3.2.1 Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line level differential analog inputs. These pins are internally
biased to the DC quiescent reference voltage, VQ, of approximately 2.7 V. The level of the signal can be
adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain Control
Registers on page 45. The ADC output data is in 2’s complement binary format. For inputs above positive
full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause
the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on page 46 to be set to
a ‘1’. The GPO pins may also be configured to indicate an overflow condition has occurred in the ADC.
See “General Purpose Pin Control (addresses 29h to 2Fh)” on page 48 for proper configuration. Figure 3
shows the full-scale analog input levels.
4.1 V
2.7 V
1.3 V
4.1 V
2.7 V
1.3 V
AIN+
AIN-
Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp
Figure 3. Full-Scale Analog Input
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