CS42436 Datasheet, PDF (40/66 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 6-out TDM CODEC

The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 400 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
5.10 Power Supply, Grounding, and PCB layout
As with any high resolution converter, the CS42436 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figures 1 to 2 show the recommended
power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be
run from the system logic supply.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42436
as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on
the same side of the board as the CS42436 to minimize inductance effects. All signals, especially clocks,
should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators.
The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the elec-
trical path from FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and
power supply arrangements.
For optimal heat dissipation from the package, it is recommended that the area directly under the part be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back-
side ground is also recommended.
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