CS42426 Datasheet, PDF (34/67 Pages) Cirrus Logic – 114 dB, 192kHz 6-Ch CODEC WITH PLL

CS42426
5.4.2 ADC FUNCTIONAL MODE (ADC_FMX)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Selects the required range of sample rates for the ADC serial port(ADC_SP). These bits must be set
to the corresponding sample rate range when the ADC_SP is in Master or Slave mode.
5.4.3 ADC CLOCK SOURCE SELECT (ADC_CLK SEL)
Default = 0
0 - ADC_SDOUT clocked from the DAC_SP.
1 - ADC_SDOUT clocked from the ADC_SP.
Function:
Selects the desired clocks for the ADC serial output.
5.4.4 DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0
Function:
Enables the digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at
the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regard-
less of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, then the
auto-detect sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-
EMPH bits in the Interrupt Control (address 1Eh) register to set the appropriate sample rate.
DAC_DEM
reg03h[1]
0
1
1
FRC_PLL_LK
reg06h[0]
X
0
1
DE-EMPH[1:0]
reg1Eh[5:4]
XX
XX
00
01
10
11
Table 6. DAC De-Emphasis
De-Emphasis
Mode
No De-Emphasis
Auto-Detect Fs
Reserved
32 kHz
44.1 kHz
48 kHz
5.5 Interface Formats (address 04h)
7
DIF1
6
DIF0
5
ADC_OL1
4
ADC_OL0
3
DAC_OL1
2
DAC_OL0
1
Reserved
0
CODEC_RJ16
5.5.1 DIGITAL INTERFACE FORMAT (DIFX)
Default = 01
Function:
These bits select the digital interface format used for the ADC & DAC Serial Port when not in one_line
mode. The required relationship between the Left/Right clock, serial clock and serial data is defined by
the Digital Interface Format and the options are detailed in Figures 7 - 9.
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