CS42426 Datasheet, PDF (12/67 Pages) Cirrus Logic – 114 dB, 192kHz 6-Ch CODEC WITH PLL

CS42426
The CS42426 is a linear phase design and does not include phase or amplitude compensation for an exter-
nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an-
alog circuitry. Figure 4 shows the full-scale analog output levels.
AOUT+
AOUT-
3.95 V
2.7 V
1.45 V
3.95 V
2.7 V
1.45 V
Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp
Figure 4. Full-Scale Output
3.3.2 Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS42426 incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is avail-
able in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate
a variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”
on page 36 is used to select which filter is used. Filter response plots can be found in Figures 32 to 55.
3.3.3 Digital Volume and Mute Control
Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to
-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h,
14h)” on page 42. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate
controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume Control (address
0Dh)” on page 40.
Each output can be independently muted via mute control bits in the register “Channel Mute (address
0Eh)” on page 41. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum
value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation
level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by
the SZC[1:0] bits.
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Con-
trol pin is tri-stated during power up or in power down mode by setting the PDN bit in the register “Power
Control (address 02h)” on page 33 to a ‘1’. Once out of power-down mode the pin can be controlled by the
user via the control port, or automatically asserted high when zero data is present on all DAC inputs, or
when serial port clock errors are present. To prevent large transients on the output, it is desirable to mute
the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descrip-
tions section for more information.
12