DDC114 Datasheet, PDF (26/30 Pages) Burr-Brown (TI) – Quad Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

DDC114
SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004
Release State
Power−Up
Initialization
Start
Integration
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CONV
Power Supplies
t₃₃
Integrate Side B
t₃₂
Figure 27. Timing Diagram at Power-Up of the DDC114
SYMBOL
t32
t33
Table 12. Timing for the DDC114 Power-Up Sequence
DESCRIPTION
MIN
TYP
MAX
Power-On Initialization Period
50
From Release Edge to Integration Start
50
UNITS
µs
µs
POWER-UP SEQUENCING
Prior to power-up, all digital and analog inputs (excluding
the complementary inputs) must be low. At the time of
power-up, all of these signals should remain low until the
power supplies have stabilized, as shown in Figure 28.
Table 12 shows the timing for the power-up sequence.
LAYOUT
POWER SUPPLIES AND GROUNDING
Both AVDD and DVDD should be as quiet as possible. It
is particularly important to eliminate noise from AVDD that
is non-synchronous with the DDC114 operation. Figure 28
illustrates two acceptable ways to supply power to the
DDC114. The first case shows two separate +5V supplies
for AVDD and DVDD. In this case, each +5V supply of the
DDC114 should be bypassed with 10µF solid tantalum
capacitors and 0.1µF ceramic capacitors. The second
case shows the DVDD power supply derived from the
AVDD supply with a < 10Ω isolation resistor. In both cases,
the 0.1µF capacitors should be placed as close to the
DDC114 package as possible. It is recommended that
both the analog and digital grounds (AGND and DGND) be
connected to a single ground plane on the PCB.
THERMAL PAD
It is strongly recommended that the thermal pad on the
DDC114 be connected to ground on the PCB. Under no
circumstances should PCB traces be routed underneath
the thermal pad.
VA
10µF
VD
10µF
AVDD
0.1µF
AGND
DDC114
DVDD
0.1µF
DGND
+5V
10µF
< 10Ω
Separate Supplies
0.1µF
AVDD AGND
DDC114
0.1µF
DVDD DGND
One +5V Supply
Figure 28. Power-Supply Connection Options
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