DDC114 Datasheet, PDF (23/30 Pages) Burr-Brown (TI) – Quad Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

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CLK
DVALID
DCLK
t₁₈
t₂₀
t₁₉
t₂₁
DIN
DDC114
SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004
t₂₀
t₂₂
t₂₃
DOUT
Input A
MSB
Input A Input B
LSB MSB
Input F Input G
LSB MSB
Input K Input L
LSB MSB
Input L
LSB
Input A
MSB
Figure 22. Timing Diagram When Using the DIN Function of the DDC114
SYMBOL
t22
t23
Table 11. Timing for the DDC114 Data Retrieval Using DIN
DESCRIPTION
MIN
TYP
MAX
Set-Up Time From DIN to Falling Edge of DCLK
5
Hold Time For DIN After Falling Edge of DCLK
4
UNITS
ns
ns
RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
Retrieval before CONV toggles is the most straightforward
method. Data retrieval begins soon after DVALID goes low
and finishes before CONV toggles; as shown in Figure 23.
For best performance, data retrieval must stop t₂₈ before
CONV toggles. This method is most appropriate for longer
integration times. The maximum time available for
readback is T_INT – t₂₇ – t₂₈. For DCLK = 10MHz and
CLK = 4MHz, the maximum number of DDC114s that can
be daisy-chained together with FORMAT = high is
calculated by Equation 1:
T_INT * 355.125ms
80t_DCLK
(1)
NOTE: 64τ_DCLK is for FORMAT = low.
Where τ_DCLK is the period of the data clock. For example,
if T_INT = 1000µs and DCLK = 10MHz, the maximum
number of DDC114s with FORMAT = high is shown in
Equation 2:
1000ms * 355.125ms
(80)(100ns)
+
80.60
³
80
DDC114s
(2)
(or 100 for FORMAT = low)
RETRIEVAL AFTER CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t₂₉ after CONV
toggles before beginning. See Figure 24 for an example of
this. The maximum time available for retrieval is
t₂₇ − t₂₉ – t₂₆ (344.875µs – 10µs – 1.75µs for
CLK = 4MHz), regardless of T_INT. The maximum number
of DDC114s that can be daisy-chained together with
FORMAT = high is calculated by Equation 3:
333.125ms
80t_DCLK
(3)
NOTE: 64τ_DCLK is for FORMAT = low.
For DCLK = 10MHz, the maximum number of DDC114s is
41. (or 52 for FORMAT = low)
23