CS4294 Datasheet, PDF (25/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
6.1.19 Extended Codec ID (Index 3Ch)
Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 ID1
ID0
1 ID1
ID0
ID[1:0]
Default
Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the configuration
pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this reg-
ister.
Mode 0 x005h
Mode 1 x000h Where x is determined by the state of ID[1:0] input pins.
The Extended Codec ID is a read/write register. Writing any value to this location issues a reset to
the Extended Codec registers (Index 3Ch-56h). The primary Audio registers are not reset by a write
to this location.
NOTE: All GPIO registers (Index 46h-54h) are reset by any write to this location.
6.1.20 Extended Codec Status/Control (Index 3Eh)
Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
0 PRH PRG
PRD PRC PRB PRA EDAC2 EADC2
1
PRG
PRC PRB PRA
EADC2
D4 D3 D2 D1 D0
EDAC1 EADC1 EREF GPIO
EADC1 EREF GPIO
PRH
PRG
PRD
PRC
PRB
PRA
EDAC2
EADC2
EDAC1
EADC1
EREF
GPIO
Default
Extended DAC2. When set powers down the Extended DAC2.
Extended ADC2. When set powers down the Extended ADC2.
Extended DAC2. When set powers down the Extended DAC1.
Extended ADC1. When set powers down the Extended ADC1.
Extended ADC/DAC Reference. When set powers down the extended ADC/DAC reference. The ex-
tended ADC/DAC and audio share a common reference. The reference will not power down unless PR3
of the Power Down Ctrl/Stat (Index 26h) register is also set.
GPIO. When set the GPIO pins are tri-state and powered down. Slot 12 is marked invalid if the AC-link
is active.
Extended DAC2. When set indicates the Extended DAC2 is ready.
Extended ADC2. When set indicates the Extended ADC2 is ready.
Extended DAC1. When set indicates the Extended DAC1 is ready.
Extended ADC1. When set indicates the Extended ADC1 is ready.
Extended ADC/DAC Reference. When set indicates the extended ADC/DAC reference is ready.
GPIO. When set the GPIO pins are ready. Slot 12 is marked valid.
Mode 0 x0CFh
Mode 1 x047h Where x is determined by the state of ID[1:0] input pins.
PR[A:D,G:H] are read/write bits that provide power management of the extended codec subsection.
All remaining bits are read/only status indicating the subsystems are ready for operation. After reset
or issuing a change to the MD[1:0] of AC Mode (Index 5Eh) register, the respective status bits for
that mode will be clear until the subsystem becomes ready.
DS326PP4
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