CS4294 Datasheet, PDF (11/42 Pages) Cirrus Logic – SoundFusion Audio/Docking Codec 97 (AMC 97)

CS4294
the next falling edge of the BIT_CLK clock signal.
The Controller is also responsible for issuing reset
via the RESET# signal. After being reset, the Co-
dec is responsible for flagging the Controller that it
is ready for operation after synchronizing its inter-
nal functions. The AC-link signals may be refer-
enced to either 5 Volts or 3.3 Volts. The CS4294
must use the same digital supply voltage as the
Controller chip.
Digital AC’97
Controller
SYNC
CODEC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
Figure 7. AC-link Connections
3.2 Control registers
All read accesses to the Codec are generated by re-
questing a register address (index number) in slot 1
of a SDATA_OUT frame. The following
SDATA_IN frame will contain the register content
in its slot 2. The write operation is identical with the
index in slot 1 and the write data in slot 2. The
AC ‘97 Frame Definition section details the func-
tion of each input and output frame. Individual reg-
ister descriptions are found in the Register
Interface section.
AC-97 Register Interface
The CS4294 implements the AC ’97 Registers in
accordance with the AC ’97 2.0 Specification. See
the Register Interface section for details on the
CS4294’s register set.
4. ANALOG SECTION
Please refer to Figure 8, Mixer diagram, for a high-
level graphical representation of the CS4294 ana-
log mixer structure.
MIC1
LINE
CD
AUX
SDATA_OUT
RESET#
SYNC
Mode Control
MAIN D/A
CONVERTERS
PCM_OUT
DAC
VOL
2
/
PCM OUT
PATH
MUTE
+20dB
VOL
MUTE
2
/
VOL
MUTE
2
/
VOL
MUTE
STEREO
INPUT
MIXER
Σ
2
/
VOL
MUTE
STEREO TO
MONO MIXER
Σ
3D
Σ
STEREO
OUTPUT
MIXER
MASTER VOLUME
VOL
OUTPUT
BUFFER
2
/
ALTERNATE VOLUME
VOL
OUTPUT
BUFFER
2
/
2
/
LINE_OUT
ALT_LINE_OUT
ADC
INPUT
MUX
MAIN ADC GAIN
VOL
MUTE
ADC
SDATA_IN
AC-Link Interface
BIT_CLK
3
/
6
/
GPIO
2
/
ADC
DAC
DS326PP4
Figure 8. Mixer Diagram
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